A typical large-scale integrated circuit (LSI) device that has recently been developed includes two or more power supply areas in a semiconductor chip and includes a circuit block in each of the power supply areas. For example, the semiconductor chip is provided with an analog circuit block that receives and processes an analog input from outside, a digital circuit block that receives and processes a digital output of the analog circuit block, and another analog circuit block that receives and processes a digital output of the digital circuit block and generates an analog output.
Such division into two or more power supply areas is performed for the reasons of that (1) the influence of noise may be reduced due to separating power supply wiring and ground wiring of the digital circuit block, in which noise affecting the power supply occurs frequently, and power supply wiring and ground wiring of the analog circuit block, in which the occurrence of noise is undesired, from each other; and that (2) power consumption of the chip may be reduced due to controlling turning on and off the power supply in each of the power supply areas.
Conventionally, an electrostatic discharge (ESD) protection circuit has been provided to prevent an internal circuit element, such as a transistor, from suffering damage resulting from an ESD applied from an external terminal. The ESD protection circuit is needed also in a semiconductor device including two or more power supply areas as described above.
A semiconductor device including two or more power supply areas is provided with an inter-circuit-block interface circuit between the power supply areas. In the interface circuit, a protection circuit against the ESD applied between different power supplies desirably includes a function different from a function of an ESD protection circuit of a conventional semiconductor device with a single power system.
The ESD protection circuit of the interface circuit provided between the power supply areas is discussed in, for example, Japanese Patent Application Laid-Open Publication No. 2006-156563 or Japanese Patent Application Laid-Open Publication No. 2007-200987. FIG. 6 of Japanese Patent Application Laid-Open Publication No. 2006-156563 illustrates a P-channel metal oxide semiconductor (PMOS) protection transistor provided between a complementary metal oxide semiconductor (CMOS) inverter on the side of an output circuit block of the interface circuit and a power supply, and an N-channel metal oxide semiconductor (NMOS) protection transistor provided between an output of the CMOS inverter and a ground power supply, and shows that the PMOS protection transistor is turned off based on a control signal from inside of an input circuit block when an ESD is applied. FIG. 24 of Japanese Patent Application Laid-Open Publication No. 2007-200987 illustrates a circuit for controlling a gate signal of a CMOS inverter on the side of an output circuit block to be held at a given level when an ESD is applied, and that when the ESD is applied, a PMOS transistor of the CMOS inverter is turned off and an NMOS transistor of the CMOS inverter is turned on.
However, when the ESD protection circuit discussed in Japanese Patent Application Laid-Open Publication No. 2006-156563 is used, such control signals need to be generated to correspond to the different power supply areas, and when the ESD protection circuit is used in an LSI device in which each circuit block is processed as different intellectual property (circuit data), a circuit designing process for the ESD protection circuit needs to be performed after an arrangement process of the circuit blocks. As a result, versatility is reduced. For example, the ESD protection circuit is desirably provided in a circuit block in each power supply area.
When the ESD protection circuit discussed in Japanese Patent Application Laid-Open Publication No. 2007-200987 is used, a circuit for the ESD protection needs to be provided for the gate terminal of the final-stage CMOS inverter on the side of the output circuit block and an output operation may be adversely affected during normal operation.